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1 ltc2481 2481f r source ( ? ) 1 +fs error (ppm) C20 0 20 1k 100k 2481 ta04 C40 C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25 c c in = 1 f direct sensor digitizer weight scales direct temperature measurement strain gauge transducers instrumentation industrial process control dvms and meters 16-bit ? adc with easy drive input current cancellation and i 2 c interface easy drive technology enables rail-to-rail inputs with zero differential input current directly digitizes high impedance sensors with full accuracy programmable gain from 1 to 256 integrated temperature sensor gnd to v cc input/reference common mode range 2-wire i 2 c interface programmable 50hz, 60hz or simultaneous 50hz/60hz rejection mode 2ppm (0.25lsb) inl, no missing codes 1ppm offset and 15ppm full-scale error selectable 2x speed mode no latency: digital filter settles in a single cycle single supply 2.7v to 5.5v operation internal oscillator six addresses available and one global address for synchronization available in a tiny (3mm 3mm) 10-lead dfn package features descriptio u applicatio s u typical applicatio u the ltc ? 2481 combines a 16-bit plus sign no latency ? tm analog-to-digital converter with patented easy drive tm tech- nology and i 2 c digital interface. the patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. this allows large external source impedances and input signals, with rail-to- rail input range to be directly digitized while maintaining exceptional dc accuracy. the ltc2481 includes on-chip programmable gain, a temperature sensor and an oscillator. the ltc2481 can be configured through an i 2 c interface to provide a program- mable gain from 1 to 256 in 8 steps, to digitize an external signal or internal temperature sensor, reject line frequen- cies (50hz, 60hz or simultaneous 50hz/60hz) as well as a 2x speed-up mode. the ltc2481 allows a wide common mode input range (0v to v cc ) independent of the reference voltage. the reference can be as low as 100mv or can be tied directly to v cc . the ltc2481 includes an on-chip trimmed oscil- lator eliminating the need for external crystals or oscilla- tors. absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration. +fs error vs r source at in + and in ltc2481 v in + ref + v cc v cc gnd v in C 1 f sda 2-wire i 2 c interface 1 f 10k i diff = 0 10k ca0/f 0 2481 ta01 ca1 scl 6 addresses ref C sense , ltc and lt are registered trademarks of linear technology corporation. no latency ? and easy drive are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patent pending.
2 ltc2481 2481f (notes 1, 2) supply voltage (v cc ) to gnd ...................... C 0.3v to 6v analog input voltage to gnd ....... C 0.3v to (v cc + 0.3v) reference input voltage to gnd .. C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) operating temperature range ltc2481c ................................................... 0 c to 70 c ltc2481i ................................................ C 40 c to 85 c storage temperature range ................ C 65 c to 125 c absolute axi u rati gs w ww u package/order i for atio uu w parameter conditions min typ max units resolution (no missing codes) 0.1 v ref v cc , Cfs v in +fs (note 5) 16 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2 10 ppm of v ref 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) 1 ppm of v ref offset error 2.5v v ref v cc , gnd in + = in C v cc (note 13) 0.5 2.5 v offset error drift 2.5v v ref v cc , gnd in + = in C v cc 10 nv/ c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref / c negative full-scale error 2.5v v ref v cc , in C = 0.75v ref , in + = 0.25v ref 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in C = 0.75v ref , in + = 0.25v ref 0.1 ppm of v ref / c total unadjusted error 5v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) 15 ppm of v ref 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 15 ppm of v ref 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) 15 ppm of v ref output noise 5v v cc 5.5v, v ref = 5v, gnd in C = in + v cc (note 12) 0.6 v rms internal ptat signal t a = 27 c 420 mv internal ptat temperature coefficient 1.4 mv/ c programmable gain see table 2a 1 256 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. LTC2481CDD ltc2481idd top view 11 dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 ca0/f 0 ca1 gnd sda scl ref + v cc ref C in + in C order part number dd part marking* lbpv t jmax = 125 c, ja = 43 c/ w exposed pad (pin 11) is gnd must be soldered to pcb the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c . (notes 3, 4) electrical characteristics ( or al speed) uw
3 ltc2481 2481f parameter conditions min typ max units resolution (no missing codes) 0.1 v ref v cc , Cfs v in +fs (note 5) 16 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2 10 ppm of v ref 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) 1 offset error 2.5v v ref v cc , gnd in + = in C v cc (note 13) 0.5 2 mv offset error drift 2.5v v ref v cc , gnd in + = in C v cc 100 nv/ c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref / c negative full-scale error 2.5v v ref v cc , in C = 0.75v ref , in + = 0.25v ref 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in C = 0.75v ref , in + = 0.25v ref 0.1 ppm of v ref / c output noise 5v v cc 5.5v, v ref = 5v, gnd in C = in + v cc 0.84 v rms programmable gain see table 2b 1 128 the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) parameter conditions min typ max units input common mode rejection dc 2.5v v ref v cc , gnd in C = in + v cc (note 5) 140 db input common mode rejection 2.5v v ref v cc , gnd in C = in + v cc (note 5) 140 db 50hz 2% input common mode rejection 2.5v v ref v cc , gnd in C = in + v cc (note 5) 140 db 60hz 2% input normal mode rejection 2.5v v ref v cc , gnd in C = in + v cc (notes 5, 7) 110 120 db 50hz 2% input normal mode rejection 2.5v v ref v cc , gnd in C = in + v cc (notes 5, 8) 110 120 db 60hz 2% input normal mode rejection 2.5v v ref v cc , gnd in C = in + v cc (notes 5, 9) 87 db 50hz/60hz 2% reference common mode 2.5v v ref v cc , gnd in C = in + v cc (note 5) 120 140 db rejection dc power supply rejection dc v ref = 2.5v, in C = in + = gnd 120 db power supply rejection, 50hz 2% v ref = 2.5v, in C = in + = gnd (notes 7, 9) 120 db power supply rejection, 60hz 2% v ref = 2.5v, in C = in + = gnd (notes 8, 9) 120 db co verter characteristics u symbol parameter conditions min typ max units in + absolute/common mode in + voltage gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage gnd C 0.3v v cc + 0.3v v fs full scale of the differential input (in + C in C ) 0.5v ref /gain v lsb least significant bit of the output code fs/2 16 v in input differential voltage range (in + C in C ) Cfs +fs v v ref reference voltage range (ref + C ref C ) 0.1 v cc v the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) a alog i put a u d refere ce uu u electrical characteristics (2x speed)
4 ltc2481 2481f symbol parameter conditions min typ max units c s (in + )in + sampling capacitance 11 pf c s (in C )in C sampling capacitance 11 pf c s (v ref )v ref sampling capacitance 11 pf i dc_leak (in + )in + dc leakage current sleep mode, in + = gnd C10 1 10 na i dc_leak (in C )in C dc leakage current sleep mode, in C = gnd C10 1 10 na i dc_leak (v ref )ref + , ref C dc leakage current sleep mode, v ref = v cc C100 1 100 na the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) a alog i put a u d refere ce uu u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 0.7v cc v v il low level input voltage 0.3v cc v v il(ca1) low level input voltage for address pin 0.05v cc v v ih(ca0/f0,ca1) high level input voltage for address pins 0.95v cc v r inh resistance from ca0/f 0 , ca1 to v cc to set 10 k ? chip address bit to 1 r inl resistance from ca1 to gnd to set 10 k ? chip address bit to 0 r inf resistance from ca0/f 0 , ca1 to v cc or 2m ? gnd to set chip address bit to float i i digital input current C10 10 a v hys hysteresis of schmitt trigger inputs (note 5) 0.05v cc v v ol low level output voltage sda i = 3ma 0.4 v t of output fall time from v ihmin to v ilmax bus load c b 10pf to 400pf (note 14) 20+0.1c b 250 ns t sp input spike suppression 50 ns i in input leakage 0.1v cc v in v cc 1 a c i capacitance for each i/o pin 10 pf c b capacitance load for each bus line 400 pf c cax external capacitive load on chip 10 pf address pins (ca0/f 0 ,ca1) for valid float v ih(ext,osc) high level ca0/f 0 external oscillator 2.7v v cc < 5.5v v cc C 0.5v v v il(ext,osc) low level ca0/f 0 external oscillator 2.7v v cc < 5.5v 0.5 v symbol parameter conditions min typ max units v cc supply voltage 2.7 5.5 v i cc supply current conversion mode (note 11) 160 250 a sleep mode (note 11) 12 a the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) power require e ts w u i 2 c digital i puts a d digital outputs u u
5 ltc2481 2481f symbol parameter conditions min typ max units f eosc external oscillator frequency range 10 4000 khz t heo external oscillator high period 0.125 100 s t leo external oscillator low period 0.125 100 s t conv_1 conversion time for 1x speed mode 50hz mode 157.2 160.3 163.5 ms 60hz mode 131.0 133.6 136.3 ms simultaneous 50hz/60hz mode 144.1 146.9 149.9 ms external oscillator (note 10) 41036/f eosc ms t conv_2 conversion time for 2x speed mode 50hz mode 78.7 80.3 81.9 ms 60hz mode 65.6 66.9 68.2 ms simultaneous 50hz/60hz mode 72.2 73.6 75.1 ms external oscillator (note 10) 20556/f eosc ms the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics w u note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2, fs = 0.5v ref /gain; v in = in + C in C , v incm = (in + + in C )/2. note 4: use internal conversion clock or external conversion clock source with f eosc = 307.2khz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: 50hz mode (internal oscillator) or f eosc = 256khz 2% (external oscillator). note 8: 60hz mode (internal oscillator) or f eosc = 307.2khz 2% (external oscillator). note 9: simultaneous 50hz/60hz mode (internal oscillator) or f eosc = 280khz 2% (external oscillator). note 10: the external oscillator is connected to the ca0/f 0 pin. the external oscillator frequency, f eosc , is expressed in khz. note 11: the converter uses the internal oscillator. note 12: the output noise includes the contribution of the internal calibration operations. note 13: guaranteed by design and test correlation. note 14: c b = capacitance of one bus line in pf. note 15: all values refer to v ih(min) and v il(max) levels. the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 15) i 2 c ti i g characteristics u w symbol parameter conditions min typ max units f scl scl clock frequency 0 400 khz t hd(sda) hold time (repeated) start condition 0.6 s t low low period of the scl clock pin 1.3 s t high high period of the scl clock pin 0.6 s t su(sta) set-up time for a repeated start condition 0.6 s t hd(dat) data hold time 0 0.9 s t su(dat) data set-up time 100 ns t r rise time for both sda and scl signals (note 14) 20+0.1c b 300 ns t f fall time for both sda and scl signals (note 14) 20+0.1c b 300 ns t su(sto) set-up time for stop condition 0.6 s
6 ltc2481 2481f typical perfor a ce characteristics uw total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) integral nonlinearity (v cc = 2.7v, v ref = 2.5v) noise histogram (6.8sps) long-term adc readings noise histogram (7.5sps) input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2481 g03 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v C45 c, 25 c, 90 c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C0.75 C0.25 0.25 0.75 2481 g05 1.25 C1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v 85 c 25 c C45 c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C0.75 C0.25 0.25 0.75 2481 g06 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v 85 c 25 c C45 c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C1.5 C0.5 0.5 1.5 2481 g04 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v 85 c 25 c C45 c output reading ( v) C3 number of readings (%) 8 10 12 0.6 2481 g07 6 4 C1.8 C0.6 C2.4 1.2 C1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v gain = 256 t a = 25 c rms = 0.60 v average = C0.69 v output reading ( v) C3 number of readings (%) 8 10 12 0.6 2481 g08 6 4 C1.8 C0.6 C2.4 1.2 C1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v gain = 256 t a = 25 c rms = 0.59 v average = C0.19 v time (hours) 0 C5 adc reading ( v) C3 C1 1 10 20 30 40 2481 g09 50 3 5 C4 C2 0 2 4 60 v cc = 5v, v ref = 5v, v in = 0v, v in(cm) = 2.5v gain = 256, t a = 25 c, rms noise = 0.60 v input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C1.5 C0.5 0.5 1.5 2481 g01 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v 85 c C45 c 25 c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2481 g02 1.25 C1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v C45 c, 25 c, 90 c
7 ltc2481 2481f typical perfor a ce characteristics uw rms noise vs input differential voltage rms noise vs v in(cm) rms noise vs temperature (t a ) rms noise vs v cc rms noise vs v ref offset error vs v in(cm) offset error vs temperature offset error vs v cc offset error vs v ref input differential voltage (v) 0.4 rms noise (ppm of v ref ) 0.6 0.8 1.0 0.5 0.7 0.9 C1.5 C0.5 0.5 1.5 2481 g10 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25 c v in(cm) (v) C1 rms noise ( v) 0.8 0.9 1.0 24 2481 g11 0.7 0.6 01 356 0.5 0.4 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd gain = 256 t a = 25 c temperature ( c) C45 0.4 rms noise ( v) 0.5 0.6 0.7 0.8 1.0 C30 C15 15 0304560 2481 g12 75 90 0.9 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd gain = 256 v cc (v) 2.7 rms noise ( v) 0.8 0.9 1.0 3.9 4.7 2481 g13 0.7 0.6 3.1 3.5 4.3 5.1 5.5 0.5 0.4 v ref = 2.5v v in = 0v v in(cm) = gnd gain = 256 t a = 25 c v ref (v) 0 0.4 rms noise ( v) 0.5 0.6 0.7 0.8 0.9 1.0 1234 2481 g14 5 v cc = 5v v in = 0v v in(cm) = gnd gain = 256 t a = 25 c v in(cm) (v) C1 offset error (ppm of v ref ) 0.1 0.2 0.3 24 2481 g15 0 C0.1 01 356 C0.2 C0.3 v cc = 5v v ref = 5v v in = 0v t a = 25 c temperature ( c) C45 C0.3 offset error (ppm of v ref ) C0.2 0 0.1 0.2 C15 15 30 90 2481 g16 C0.1 C30 0 45 60 75 0.3 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd v cc (v) 2.7 offset error (ppm of v ref ) 0.1 0.2 0.3 3.9 4.7 2481 g17 0 C0.1 3.1 3.5 4.3 5.1 5.5 C0.2 C0.3 ref + = 2.5v ref C = gnd v in = 0v v in(cm) = gnd t a = 25 c v ref (v) 0 C0.3 offset error (ppm of v ref ) C0.2 C0.1 0 0.1 0.2 0.3 1234 2481 g18 5 v cc = 5v ref C = gnd v in = 0v v in(cm) = gnd t a = 25 c
8 ltc2481 2481f typical perfor a ce characteristics uw temperature sensor vs temperature temperature sensor error vs temperature on-chip oscillator frequency vs temperature on-chip oscillator frequency vs v cc psrr vs frequency at v cc psrr vs frequency at v cc conversion current vs temperature sleep mode current vs temperature psrr vs frequency at v cc temperature ( c) C60 temperature error ( c) 1 3 5 60 2481 g20 C1 C3 0 2 4 C2 C4 C5 C30 0 30 90 120 v cc = 5v v ref = 1.4v temperature ( c) C45 C30 300 frequency (khz) 304 310 C15 30 45 2481 g21 302 308 306 15 0 60 75 90 v cc = 4.1v v ref = 2.5v v in = 0v v in(cm) = gnd v cc (v) 2.5 300 frequency (khz) 302 304 306 308 310 3.0 3.5 4.0 4.5 2481 g22 5.0 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd frequency at v cc (hz) 1 0 C20 C40 C60 C80 C100 C120 C140 1k 100k 2481 g23 10 100 10k 1m rejection (db) v cc = 4.1v dc v ref = 2.5v in + = gnd in C = gnd t a = 25 c frequency at v cc (hz) 0 C140 rejection (db) C120 C80 C60 C40 0 20 100 140 2481 g24 C100 C20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v v ref = 2.5v in + = gnd in C = gnd t a = 25 c temperature ( c) C45 100 conversion current ( a) 120 160 180 200 C15 15 30 90 2481 g26 140 C30 0 45 60 75 v cc = 5v v cc = 2.7v temperature ( c) C45 0 sleep mode current ( a) 0.2 0.6 0.8 1.0 2.0 1.4 C15 15 30 90 2481 g27 0.4 1.6 1.8 1.2 C30 0 45 60 75 v cc = 5v v cc = 2.7v frequency at v cc (hz) 30600 C60 C40 0 30750 2481 g25 C80 C100 30650 30700 30800 C120 C140 C20 rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in C = gnd t a = 25 c temperature ( c) C60 v ptat /v ref (v) 0.35 0.40 120 2481 g19 0.30 0.20 30 090 C30 60 0.25 v cc = 5v v ref = 1.4v
9 ltc2481 2481f input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2481 g31 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v 90 c C45 c, 25 c typical perfor a ce characteristics uw conversion current vs output data rate integral nonlinearity (2x speed mode; v cc = 5v, v ref = 5v) integral nonlinearity (2x speed mode; v cc = 5v, v ref = 2.5v) integral nonlinearity (2x speed mode; v cc = 2.7v, v ref = 2.5v) noise histogram (2x speed mode) rms noise vs v ref (2x speed mode) offset error vs v in(cm) (2x speed mode) offset error vs temperature (2x speed mode) input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2481 g30 1.25 C1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v 90 c C45 c, 25 c output reading ( v) 179 number of readings (%) 8 10 12 186.2 2481 g32 6 4 181.4 183.8 188.6 2 0 16 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v gain = 256 t a = 25 c rms = 0.86 v average = 0.184mv v ref (v) 0 rms noise ( v) 0.6 0.8 1.0 4 2481 g33 0.4 0.2 0 1 2 3 5 v cc = 5v v in = 0v v in(cm) = gnd t a = 25 c v in(cm) (v) C1 180 offset error ( v) 182 186 188 190 200 194 1 3 4 2481 g34 184 196 198 192 0 2 5 6 v cc = 5v v ref = 5v v in = 0v t a = 25 c temperature ( c) C45 offset error ( v) 200 210 220 75 2481 g35 190 180 160 C15 15 45 C30 90 0 30 60 170 240 230 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd output data rate (readings/sec) 0 supply current ( a) 500 450 400 350 300 250 200 150 100 80 2481 g28 20 40 60 100 70 10 30 50 90 v cc = 5v v cc = 3v v ref = v cc in + = gnd in C = gnd ca0/f 0 = ext osc t a = 25 c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C1.5 C0.5 0.5 1.5 2481 g29 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v 25 c, 90 c C45 c
10 ltc2481 2481f ref + (pin 1), ref (pin 3): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is more positive than the reference negative input, ref C , by at least 0.1v. v cc (pin 2): positive supply voltage. bypass to gnd (pin 8) with a 1 f tantalum capacitor in parallel with 0.1 f ceramic capacitor as close to the part as possible. in + (pin 4), in (pin 5): differential analog input. the voltage on these pins can have any value between typical perfor a ce characteristics uw offset error vs v cc (2x speed mode) offset error vs v ref (2x speed mode) psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode) uu u pi fu ctio s v cc (v) 2.7 0 offset error ( v) 100 250 3 4 4.5 2481 g36 50 200 150 3.5 5 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd t a = 25 c v ref (v) 0 offset error ( v) 190 200 210 3 5 2481 g37 180 170 160 12 4 220 230 240 v cc = 5v v in = 0v v in(cm) = gnd t a = 25 c frequency at v cc (hz) 1 0 C20 C40 C60 C80 C100 C120 C140 1k 100k 2481 g38 10 100 10k 1m rejection (db) v cc = 4.1v dc ref + = 2.5v ref C = gnd in + = gnd in C = gnd t a = 25 c frequency at v cc (hz) 0 C140 rrejection (db) C120 C80 C60 C40 0 20 100 140 2481 g39 C100 C20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v ref + = 2.5v ref C = gnd in + = gnd in C = gnd t a = 25 c frequency at v cc (hz) 30600 C60 C40 0 30750 2481 g40 C80 C100 30650 30700 30800 C120 C140 C20 rejection (db) v cc = 4.1v dc 0.7v ref + = 2.5v ref C = gnd in + = gnd in C = gnd t a = 25 c gnd C 0.3v and v cc + 0.3v. within these limits the converter bipolar input range (v in = in + C in C ) extends from C0.5 ? v ref /gain to 0.5 ? v ref /gain. outside this input range the converter produces unique overrange and underrange output codes. scl (pin 6): serial clock pin of the i 2 c interface. the ltc2481 can only act as a slave and the scl pin only accepts external serial clock. data is shifted into the sda pin on the rising edges of the scl clock and output through the sda pin on the falling edges of the scl clock.
11 ltc2481 2481f uu u pi fu ctio s uu w fu ctio al block diagra sda (pin 7): bidirectional serial data line of the i 2 c interface. in the transmitter mode (read), the conversion result is output through the sda pin, while in the receiver mode (write), the device configuration bits are input through the sda pin. at data input mode, the pin is high impedance; while at data output mode, it is an open-drain n-channel driver and therefore an external pull-up resistor or current source to v cc is needed. gnd (pin 8): ground. connect this pin to a ground plane through a low impedance connection. ca1 (pin 9): chip address control pin. the ca1 pin is configured as a three state (low, high, or floating) address control bit for the device i 2 c address. ca0/f 0 (pin 10): chip address control pin/external clock input pin. when no transition is detected on the ca0/f 0 pin, it is a two state (high or floating) address control bit for the device i 2 c address. when the pin is driven by an external clock signal with a frequency f eosc of at least 10khz, the converter uses this signal as its system clock and the fundamental digital filter rejection null is located at a frequency f eosc /5120 and sets the chip address ca0 internally to a high. 6 7 4 5 9 10 3rd order ? adc ref + in + in + 1 ref + in C in C ref C (1-256) gain i 2 c serial interface temp sensor mux scl 2 v cc 3 ref C 8 gnd ca0/f 0 2481 fd sda ca1 autocalibration and control internal oscillator
12 ltc2481 2481f applicatio s i for atio wu uu figure 1. ltc2481 state transition diagram conversion power on reset default configuration: external input gain = 1 50/60hz rejection 1x speed, autocal sleep 2481 f01 yes no acknowledge yes no stop or read 24-bits data output/input converter operation converter operation cycle the ltc2481 is a low power, ? analog-to-digital con- verter with an i 2 c interface. after power on reset, its operation is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output/ input (see figure 1). initially, the ltc2481 performs a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced by two orders of magnitude. the part remains in the sleep state as long as it is not addressed for a read/write operation. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. the device will not acknowledge an external request during the conversion state. after a conversion is finished, the device is ready to accept a read/write request. once the ltc2481 is addressed for a read operation, the device begins outputting the conversion result under control of the serial clock (scl). there is no latency in the conver- sion result. the data output is 24 bits long and contains a16-bit plus sign conversion result plus a readback of the configuration bits corresponds to the conversion just performed. this result is shifted out on the sda pin under the control of the scl. data is updated on the falling edges of scl allowing the user to reliably latch data on the rising edge of scl. in write operation, the device accepts one configuration byte and the data is shifted in on the rising edges of the scl. a new conversion is initiated by a stop condition following a valid write operation or at the con- clusion of a data read operation (read out all 24 bits). i 2 c interface the ltc2481 communicates through an i 2 c interface. the i 2 c interface is a 2-wire open-drain interface sup- porting multiple devices and masters on a single bus. the connected devices can only pull the bus wires low and can never drive the bus high. the bus wires are exter- nally connected to a positive supply voltage via a current- source or pull-up resistor. when the bus is free, both lines are high. data on the i 2 c-bus can be transferred at rates of up to 100kbit/s in the standard-mode and up to 400kbit/s in the fast-mode. each device on the i 2 c bus is recognized by a unique address stored in that device and can operate as either a transmitter or receiver, depending on the function of the device. in addition to transmitters and receivers, devices can also be considered as masters or slaves when per- forming data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. at the same time any device addressed is considered a slave.
13 ltc2481 2481f applicatio s i for atio wu uu figure 2. definition of timing for f/s-mode devices on the i 2 c-bus the ltc2481 can only be addressed as a slave. once addressed, it can receive configuration bits or transmit the last conversion result. therefore the serial clock line scl is an input only and the data line sda is bidirectional. the device supports the standard-mode and the fast-mode for data transfer speeds up to 400kbit/s. figure 2 shows the definition of timing for fast/standard-mode devices on the i 2 c-bus. the start and stop conditions a start condition is generated by transitioning sda from high to low while scl is high. the bus is considered to be busy after the start condition. when the data transfer is finished, a stop condition is generated by transitioning sda from low to high while scl is high. the bus is free again a certain time after the stop condition. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the repeated start (sr) conditions are functionally identical to the start (s). data transferring after the start condition, the i 2 c bus is busy and data transfer is set between a master and a slave. data is transferred over i 2 c in groups of nine bits (one byte) followed by an acknowledge bit, therefore each group takes nine scl cycles. the transmitter releases the sda line during the acknowledge clock pulse and the receiver issues an acknowledge (ack) by pulling sda low or leaves sda high to indicate a not acknowledge (nak) condition. change of data state can only happen while scl is low. accessing the special features of the ltc2481 the ltc2481 combines a high resolution, low noise ? analog-to-digital converter with an on-chip selectable tem- perature sensor, programmable gain, programmable digital filter and output rate control. these special features are selected through a single 8-bit serial input word during the data input/output cycle (see figure 3). the ltc2481 powers up in a default mode commonly used for most measurements. the device will remain in this mode until a valid write cycle is performed. in this default mode, the measured input is external, the gain is 1, the digital filter simultaneously rejects 50hz and 60hz line frequency noise, and the speed mode is 1x (offset automatically, continuously calibrated). the i 2 c serial interface grants access to any or all special functions contained within the ltc2481. in order to change the mode of operation, a valid write address followed by 8 bits of data are shifted into the device (see table 1). the first 3 bits (gs2, gs1, gs0) control the gain of the converter from 1 to 256. the 4th bit is reserved and should be low. the 5th bit (im) is used to select the internal temperature sensor as the conversion input, while the 6th and 7th bits (fa, fb) combine to determine the line frequency rejection mode. the 8th bit (spd) is used to double the output rate by disabling the offset auto calibration. sda scl ssrps t f t low t hd;sta t hd;sta t buf t sp t su;sta t su;sto t hd;dat t high t su;da t t r t r t r 24 8 1 f02
14 ltc2481 2481f applicatio s i for atio wu uu table 1. selecting special modes figure 3. timing diagram for writing to the ltc2481 gs2 gs1 gain any gain 2481 tbl1 any speed any rejection mode gs0 x x x x x x x x x x x x x x x x 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 im fa fb spd external input, gain = 1, autocalibration external input, gain = 4, autocalibration external input, gain = 8, autocalibration external input, gain = 16, autocalibration external input, gain = 32, autocalibration external input, gain = 64, autocalibration external input, gain = 128, autocalibration external input, gain = 256, autocalibration external input, gain = 1, 2x speed external input, gain = 2, 2x speed external input, gain = 4, 2x speed external input, gain = 8, 2x speed external input, gain = 16, 2x speed external input, gain = 32, 2x speed external input, gain = 64, 2x speed external input, gain = 128, 2x speed external input, simultaneous 50hz/60hz rejection external input, 50hz rejection external input, 60hz rejection reserved, do not use temperature input, 50hz/60hz rejection, gain = 1, autocalibration temperature input, 50hz rejection, gain = 1, autocalibration temperature input, 60hz rejection, gain = 1, autocalibration reserved, do not use 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 rejection mode comments sda scl gs2 gs1 gs0 im fa fb spd w sleep data input 7 8 9 1 2 3 4 5 6 7 8 9 1 2 start by master 7-bit address ack by ltc24 8 1 ack by ltc24 8 1 24 8 1 f03
15 ltc2481 2481f applicatio s i for atio wu uu table 2b. the ltc2481 performance vs gain in 2x speed mode (v cc = 5v, v ref = 5v) gain 1248163264128 unit input span 2.5 1.25 0.625 0.312 0.156 78m 39m 19.5m v lsb 38.1 19.1 9.54 4.77 2.38 1.19 0.596 0.298 v noise free resolution* 65536 65536 65536 65536 65536 65536 45875 22937 counts gain error 55555555ppm of fs offset error 200 200 200 200 200 200 200 200 v *the resolution in counts is calculated as the fs divided by lsb or the rms noise value, whichever is larger. table 2a. the ltc2481 performance vs gain in normal speed mode (v cc = 5v, v ref = 5v) gain 1 4 8 16 32 64 128 256 unit input span 2.5 0.625 0.312 0.156 78m 39m 19.5m 9.76m v lsb 38.1 9.54 4.77 2.38 1.19 0.596 0.298 0.149 v noise free resolution* 65536 65536 65536 65536 65536 65536 32768 16384 counts gain error 55555558ppm of fs offset error 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 v gain (gs2, gs1, gs0) the input referred gain of the ltc2481 is adjustable from 1 to 256. with a gain of 1, the differential input range is v ref /2 and the common mode input range is rail-to-rail. as the gain is increased, the differential input range is reduced to v ref /2 ? gain but the common mode input range remains rail-to-rail. as the differential gain is in- creased, low level voltages are digitized with greater resolution. at a gain of 256, the ltc2481 digitizes an input signal range of 9.76mv with over 16,000 counts. temperature sensor (im) the ltc2481 includes an on-chip temperature sensor. the temperature sensor is selected by setting im = 1 in the serial input data stream. conversions are performed directly on the temperature sensor by the converter. while operating in this mode, the device behaves as a temperature to bits converter. the digital reading is proportional to the abso- lute temperature of the device. this feature allows the converter to linearize temperature sensors or continuously remove temperature effects from external sensors. several applications leveraging this feature are presented in more detail in the applications section. while operating in this mode, the gain is set to 1 and the speed is set to normal in- dependent of the control bits (gs2, gs1, gs0 and spd). rejection mode (fa, fb) the ltc2481 includes a high accuracy on-chip oscillator with no required external components. coupled with a 4th order digital lowpass filter, the ltc2481 rejects line fre- quency noise. in the default mode, the ltc2481 simulta- neously rejects 50hz and 60hz by at least 87db. the ltc2481 can also be configured to selectively reject 50hz or 60hz to better than 110db. speed mode (spd) the ltc2481 continuously performs offset calibrations. every conversion cycle, two conversions are automati- cally performed (default) and the results combined. this result is free from offset and drift. in applications where the offset is not critical, the autocalibration feature can be disabled with the benefit of twice the output rate. linearity, full-scale accuracy and full-scale drift are iden- tical for both 2x and 1x speed modes. in both the 1x and 2x speed there is no latency. this enables input steps or multiplexer channel changes to settle in a single conversion cycle easing system overhead and increasing the effective conversion rate.
16 ltc2481 2481f table 3. ltc2481 status bits bit 23 bit 22 input range sig msb v in 0.5 ? v ref 11 0v v in < 0.5 ? v ref 10 C0.5 ? v ref v in < 0v 0 1 v in < C 0.5 ? v ref 00 (msb) of the result. the first two bits (sig and msb) can be used to indicate over range conditions. if both bits are high, the differential input voltage is above +fs and the following 16 bits are set to low to indicate an overrange condition. if both bits are low, the input voltage is below Cfs and the following 16 bits are set to high to indicate an underrange condition. the function of these two bits is summarized in table 3. the next 16 bits contain the conversion results in binary twos complement format. the remaining six bits are a readback of the configuration register. as long as the voltage on the in + and in C pins is main- tained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref /gain to +fs = 0.5 ? v ref /gain. for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. applicatio s i for atio wu uu ltc2481 data format after a start condition, the master sends a 7-bit address followed by a r/w bit. the bit r/w is 1 for a read request and 0 for a write request. if the 7-bit address agrees with an ltc2481s address, that device is selected. when the device is in the conversion state, it does not accept the request and issues a not-acknowledge (nak) by leaving sda high. if the conversion is complete, it issues an acknowledge (ack) by pulling sda low. the ltc2481 has two registers. the output register contains the result of the last conversion and a user programmable configuration register that sets the con- verter operation mode. the output register contains the last conversion result. after each conversion is completed, the device automati- cally enters the sleep state where the supply current is reduced to 1 a. when the ltc2481 is addressed for a read operation, it acknowledges (by pulling sda low) and acts as a transmitter. the master and receiver can read up to three bytes from the ltc2481. after a complete read operation (3 bytes), the output register is emptied, a new conversion is initiated, and a following read request in the same input/output phase will be naked. the ltc2481 output data stream is 24 bits long, shifted out on the falling edges of scl. the first bit is the conversion result sign bit (sig), see tables 3 and 4. this bit is high if v in 0. it is low if v in <0. the second bit is the most significant bit table 4. ltc2481 output data format differential input voltage bit 23 bit 22 bit 21 bit 20 bit 19 bit 6 v in * sig msb v in * fs** 1 1 0 0 0 0 fs** C 1lsb 1 0 1 1 1 1 0.5 ? fs** 1 0 1 0 0 0 0.5 ? fs** C 1lsb 1 0 0 1 1 1 0100000 C1lsb 0 1 1 1 1 1 C 0.5 ? fs** 0 1 1 0 0 0 C 0.5 ? fs** C 1lsb 0 1 0 1 1 1 C fs** 0 1 0 0 0 0 v in * < Cfs** 0 0 1 1 1 1 *the differential input voltage v in = in + C in C . **the full-scale voltage fs = 0.5 ? v ref /gain.
17 ltc2481 2481f initiating a new conversion when the ltc2481 finishes a conversion, it automatically enters the sleep state. once in the sleep state, the device is ready for read/write operations. after the device ac- knowledges a read or write request, the device exits the sleep state and enters the data input/output state. the data input/output state concludes and the ltc2481 starts a new conversion once a stop condition is issued by the master or all 24-bits of data are read out of the device. during the data read cycle, a stop command may be issued by the master controller in order to start a new conversion and abort the data transfer. this stop command must be issued during the 9th clock cycle of a byte read when the bus is free (the ack/nak cycle). ltc2481 address the ltc2481 has two address pins, enabling one in 6 possible addresses, as shown in table 5. table 5. ltc2481 address assignment ca1 ca0/f 0 * address low high 001 01 00 low floating 001 01 01 floating high 001 01 11 floating floating 010 01 00 high high 010 01 10 high floating 010 01 11 * ca0/f 0 is treated as high when driven by a valid external clock. in addition to the configurable addresses listed in table 5, the ltc2481 also contains a global address (1110111) which may be used for synchronizing multiple ltc2481s. operation sequence the ltc2481 acts as a transmitter or receiver. the device may be programmed to perform several functions. these include measuring an external differential input signal or an integrated temperature sensor, setting a program- mable gain (from 1 to 256), selecting line frequency rejection (50hz, 60hz, or simultaneous 50hz and 60hz), and a 2x speed up mode. continuous read in applications where the configuration does not need to change for each conversion cycle, the conversion result can be continuously read. the configuration remains unchanged from the last value written into the device. if the device has not been written to since power up, the configuration is set to the default value (input external, gain=1, simultaneous 50hz/60hz rejection, and 1x speed mode). the operation sequence is shown in figure 6. when the conversion is finished, the device may be addressed for a read operation. at the end of a read operation, a new conversion begins. at the conclusion of the conversion cycle, the next result may be read using the method described above. if the conversion cycle is not concluded and a valid address selects the device, the ltc2481 generates a nak signal indicating the conversion cycle is in progress. applicatio s i for atio wu uu figure 4. timing diagram for reading from the ltc2481 sleep data output start by master ack by ltc24 8 1 ack by master nak by master pg2 pg1 pg0 x im spd lsb r msb sgn d15 7 8 9 1 2 9 1 2 3 4 5 6 7 8 9 1 7-bit address 24 8 1 f04
18 ltc2481 2481f applicatio s i for atio wu uu continuous read/write once the conversion cycle is concluded, the ltc2481 can be written to then read from, using the repeated start (sr) command. figure 7 shows a cycle which begins with a data write, a repeated start, followed by a read, and concluded with a stop command. the following conversion begins after all 24-bits are read out of the device or after the stop command and uses the newly programmed configura- tion data. discarding a conversion result and initiating a new conversion with optional configuration updating at the conclusion of a conversion cycle, a write cycle can be initiated. once the write cycle is acknowledged, a stop (p) command initiates a new conversion. if a new configuration is required, this data can be written into the device and a stop command initiates a new conversion, see figure 8. figure 5. the ltc2481 conversion sequence 7-bit address conversion conversion conversion sleep sleep data output data output 7-bit address ss rr ack ack read read pp 24 8 1 f06 figure 6. consecutive reading at the same configuration 7-bit address conversion conversion address sleep data output data input 7-bit address s r w ack ack write sr p read 24 8 1 f0 8 figure 7. write, read, start conversion synchronizing multiple ltc2481s with the global address call in applications where several ltc2481s are used on the same i 2 c bus, all ltc2481s can be synchronized with the global address call. to achieve this, first all the ltc2481s must have completed the conversion cycle. the master issues a start, followed by the ltc2481 global address 1110111 and a write request. all ltc2481s will be selected and acknowledge the request. the master then sends the write byte (optional) and ends the write operation with a stop. this will update the configuration registers (if a write byte was sent) and initiate a new conversion simul- taneously on all the ltc2481s, as shown in figure 9. in order to synchronize the start of conversion without affecting the configuration registers, the write operation can be aborted with a stop. this initiates a new conversion on all the ltc2481s without changing the configuration registers. s ack data sr data transferring p sleep data input/output conversion conversion 7-bit address r/w 2481 f05
19 ltc2481 2481f easy drive input current cancellation the ltc2481 combines a high precision delta-sigma adc with an automatic differential input current cancellation front end. a proprietary front-end passive sampling network transparently removes the differential input cur- rent. this enables external rc networks and high imped- ance sensors to directly interface to the ltc2481 without external amplifiers. the remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see automatic input current cancellation section). this unique architec- ture does not require on-chip buffers enabling input signals to swing all the way to ground and up to v cc . furthermore, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity) is main- tained even with external rc networks. conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). for high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50hz or 60hz plus their harmonics. the filter rejection performance is directly re- lated to the accuracy of the converter system clock. the ltc2481 incorporates a highly accurate on-chip oscillator. this eliminates the need for external frequency setting com- ponents such as crystals or oscillators. frequency rejection selection (ca0/f 0 ) the ltc2481 internal oscillator provides better than 110db normal mode rejection at the line frequency and all its harmonics (up to the 255th) for 50hz 2% or 60hz 2%, or better than 87db normal mode rejection from 48hz to 62.4hz. the rejection mode is selected by writing to the on-chip configuration register (the default mode at power up is simultaneous 50hz/60hz rejection). when a fundamental rejection frequency different from 50hz or 60hz is required or when the converter must be synchronized with an outside source, the ltc2481 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the ca0/f 0 pin and turns off the internal oscilla- tor. the chip address for ca0 is internally set high. the frequency f eosc of the external signal must be at least 10khz to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t heo and t leo are observed. applicatio s i for atio wu uu figure 8. start a new conversion without reading old conversion result global address scl sda ltc24 8 1 ltc24 8 1 ltc24 8 1 all ltc24 8 1s in sleep conversion of all ltc24 8 1s data input s w ack write (optional) p 24 8 1 f10 figure 9. synchronize the ltc2481s with the global address call 7-bit address conversion conversion sleep data input s w ack write (optional) p 24 8 1 f09
20 ltc2481 2481f while operating with an external conversion clock of a frequency f eosc , the ltc2481 provides better than 110db normal mode rejection in a frequency range of f eosc /5120 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc /5120 is shown in figure 10. whenever an external clock is not present at the ca0/f 0 pin, the converter automatically activates its internal os- cillator and enters the internal conversion clock mode. ca0/f 0 may be tied high or left floating in order to set the chip address. the ltc2481 operation will not be dis- turbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. table 6 summarizes the duration of the conversion state of each state and the achievable output data rate as a function of f eosc . ease of use the ltc2481 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. the ltc2481 performs offset and full-scale calibrations every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation described applicatio s i for atio wu uu above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. power-up sequence the ltc2481 automatically enters an internal reset state when the power supply voltage v cc drops below approxi- mately 2v. this feature guarantees the integrity of the conver- sion result. when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 4ms. the por signal clears all internal registers. following the por signal, the ltc2481 starts a normal conversion cycle and follows the succession of states described in figure 1. the figure 10. ltc2481 normal mode rejection when using an external oscillator differential input signal frequency deviation from notch frequency f eosc /5120(%) C12C8C404812 normal mode rejection (db) 2481 f11 C80 C85 C90 C95 C100 C105 C110 C115 C120 C125 C130 C135 C140 table 6. ltc2481 state duration state operating mode duration conversion internal oscillator 60hz rejection 133ms, output data rate 7.5 readings/s for 1x speed mode 67ms, output data rate 15 readings/s for 2x speed mode 50hz rejection 160ms, output data rate 6.2 readings/s for 1x speed mode 80ms, output data rate 12.5 readings/s for 2x speed mode 50hz/60hz rejection 147ms, output data rate 6.8 readings/s for 1x speed mode 73.6ms, output data rate 13.6 readings/s for 2x speed mode external oscillator ca0/f 0 = external oscillator 41036/f eosc s, output data rate f eosc /41036 readings/s for with frequency f eosc hz 1x speed mode (f eosc /5120 rejection) 20556/f eosc s, output data rate f eosc /20556 readings/s for 2x speed mode
21 ltc2481 2481f applicatio s i for atio wu uu first conversion result following por is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. on-chip temperature sensor the ltc2481 contains an on-chip ptat (proportional to absolute temperature) signal that can be used as a tempera- ture sensor. the internal ptat has a typical value of 420mv at 27 c and is proportional to the absolute temperature value with a temperature coefficient of 420/(27 + 273) = 1.40mv/ c (slope), as shown in figure 11. the internal ptat signal is used in a single-ended mode referenced to device ground internally. the gain is automatically set to one (independent of the values of gs0, gs1, gs2) in order to preserve the ptat property at the adc output code and avoid an out of range error. the 1x speed mode with auto- matic offset calibration is automatically selected for the in- ternal ptat signal measurement as well. when using the internal temperature sensor, if the output code is normalized to r sda = v ptat /v ref , the temperature is calculated using the following formula: if the same v ref source is used during calibration and temperature measurement, the actual value of the v ref is not needed to measure the temperature as shown in the calculation below: slope rv t sda ref = + 0 0 273 ? t rv slope r r t c sda ref sda sda = =+ () ? C ?C 273 0 0 273 273 figure 11. internal ptat signal vs temperature temperature ( c) C60 v ptat (mv) 500 600 120 2481 f12 400 200 30 090 C30 60 300 v cc = 5v im = 1 slope = 1.40mv/ c where slope is nominally 1.4mv/ c. since the ptat signal can have an initial value variation which results in errors in slope, to achieve absolute temperature measurements, a one-time calibration is needed to adjust the slope value. the converter output of the ptat signal, r0 sda , is measured at a known tempera- ture t0 (in c) and the slope is calculated as: this calibrated slope can be used to calculate the temperature. reference voltage range the ltc2481 external reference voltage range is 0.1v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference volt- age. since the transition noise (600nv) is much less than the quantization noise (v ref /2 17 ), a decrease in the refer- ence voltage will increase the converter resolution. a reduced reference voltage will also improve the converter performance when operated with an external conversion clock (external f o signal) at substantially higher output data rates (see the output data rate section). v ref must be 1.1v to use the internal temperature sensor. the reference input is differential. the differential refer- ence input range (v ref = ref + C ref C ) is 100mv to v cc and the common mode reference input range is 0v to v cc . t rv slope t rv slope k sda ref c sda ref = = ? ? C in kelvin and in c 273
22 ltc2481 2481f input voltage range the analog input is truly differential with an absolute/ common mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2481 converts the bipolar differential input signal, v in = in + C in C , from C fs to +fs where fs = 0.5 ? v ref /gain. beyond this range, the converter indicates the overrange or the underrange con- dition using distinct output codes. since the differential input current cancellation does not rely on an on-chip buffer, current cancellation as well as dc performance is maintained rail-to-rail. i nput signals applied to in + and in C pins may extend by 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the in + and in C pins without affecting the perfor- mance of the devices. the effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the input current/reference current sec- tions. in addition, series resistors will introduce a tem- perature dependent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. applicatio s i for atio wu uu driving the input and reference the input and reference pins of the ltc2481 converter are directly connected to a network of sampling capacitors. depending upon the relation between the differential input voltage and the differential reference voltage, these capaci- tors are switching between these four pins transferring small amounts of charge in the process. a simplified equiva- lent circuit is shown in figure 12. for a simple approximation, the source impedance r s driving an analog input pin (in + , in C , ref + or ref C ) can be considered to form, together with r sw and c eq (see figure 12), a first order passive network with a time con- stant = (r s + r sw ) ? c eq . the converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant . the sampling process on the four input analog pins is quasi-independent so each time con- stant should be considered by itself and, under worst-case circumstances, the errors may add. when using the internal oscillator, the ltc2481s front- end switched-capacitor network is clocked at 123khz corresponding to an 8.1 s sampling period. thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that 8.1 s/14 = 580ns. when an external oscillator of frequency f eosc is used, the sampling period is 2.5/f eosc and, for a settling error of less than 1ppm, 0.178/f eosc . v ref + v in + v cc r sw (typ) 10k i leak i leak v cc i leak i leak v cc r sw (typ) 10k c eq 12pf (typ) r sw (typ) 10k i leak i in + v in C i in C i ref + i ref C 2480 f13 i leak v cc i leak i leak switching frequency f sw = 123khz internal oscillator f sw = 0.4 ? f eosc external oscillator v ref C r sw (typ) 10k iin iin vv r i ref vv v r v vr vd r vv v r v vr where avg avg in cm ref cm eq avg ref incm refcm eq in ref eq ref t eq ref ref cm in cm eq in ref eq + + ref + ref C () = () = ? ? () = ? ? + ? ? ? ?? + () C () () () () . . . .? ? .C .? C ? 05 15 05 05 15 05 2 2 : . v vinin v in in r m internal oscillator hz mode refcm in incm eq = = ? = + ? ? ? ? ? ? ? = = ? =? () + ? + ? v , ref = ref + ref C + ? ? ? ? ? ? 2 2 271 60 ? r 2.98m internal oscillator 50hz and 60hz mode r 0.833 10 / f external oscillator d is the density of a digital transition at the modulator output eq eq 12 eosc t where ref C is internally tied to gnd figure 12. ltc2481 equivalent analog input circuit
23 ltc2481 2481f automatic differential input current cancellation in applications where the sensor output impedance is low (up to 10k ? with no external bypass capacitor or up to 500 ? with 0.001 f bypass), complete settling of the input occurs. in this case, no errors are introduced and direct digitization of the sensor is possible. for many applications, the sensor output impedance com- bined with external bypass capacitors produces rc time constants much greater than the 580ns required for 1ppm accuracy. for example, a 10k ? bridge driving a 0.1 f bypass capacitor has a time constant several orders of magnitude greater than the required maximum. histori- cally, settling issues were solved using buffers. these buffers led to increased noise, reduced dc performance (offset/drift), limited input/output swing (cannot digitize signals near ground or v cc ), added system cost and in- creased power. the ltc2481 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. this allows accurate direct digitization of high impedance sensors without the need of buffers (see figures 13 to 15). addi- tional errors resulting from mismatched leakage currents must also be taken into account. the switching algorithm forces the average input current on the positive input (i in + ) to be equal to the average input current on the negative input (i in C ). over the complete conversion cycle, the average differential input current (i in + C i in C ) is zero. while the differential input current is zero, the common mode input current (i in + + i in C )/2 is proportional to the difference between the common mode input voltage (v incm ) and the common mode reference voltage (v refcm ). in applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balance bridge type application, both the differ- ential and common mode input current are zero. the accuracy of the converter is unaffected by settling errors. mismatches in source impedances between in + and in C also do not affect the accuracy. in applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while applicatio s i for atio wu uu c ext 2481 f14 v incm + 0.5v in r source in + ltc2481 c par ? 20pf c ext v incm C 0.5v in r source in C c par ? 20pf figure 13. an rc network at in + and in r source ( ? ) 1 +fs error (ppm) C20 0 20 1k 100k 2481 f15 C40 C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v t a = 25 c c ext = 0pf c ext = 100pf c ext = 1nf, 0.1 f, 1 f figure 14. +fs error vs r source at in + and in r source ( ? ) 1 Cfs error (ppm) C20 0 20 1k 100k 2481 f16 C40 C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v t a = 25 c c ext = 0pf c ext = 100pf c ext = 1nf, 0.1 f, 1 f figure 15. ?s error vs r source at in + and in the common mode input current is proportional to the difference between v incm and v refcm . for a reference common mode of 2.5v and an input common mode of 1.5v, the common mode input current is approximately
24 ltc2481 2481f 0.74 a (in simultaneous 50hz/60hz rejection mode). this common mode input current has no effect on the accuracy if the external source impedances tied to in + and in C are matched. mismatches in these source impedances lead to a fixed offset error but do not affect the linearity or full- scale reading. a 1% mismatch in 1k ? source resistances leads to a 15ppm shift (74 v) in offset voltage. in applications where the common mode input voltage varies as a function of input signal level (single-ended input, rtds, half bridges, current sensors, etc.), the common mode input current varies proportionally with input voltage. for the case of balanced input impedances, the common mode input current effects are rejected by the large cmrr of the ltc2481 leading to little degradation in accuracy. mismatches in source impedances lead to gain errors proportional to the difference between the common mode input voltage and the common mode reference voltage. 1% mismatches in 1k ? source resistances lead to worst-case gain errors on the order of 15ppm or 1lsb (for 1v differences in reference and input common mode voltage). table 7 summarizes the effects of mismatched source impedance and differences in reference/input com- mon mode voltages. table 7. suggested input configuration for ltc2481 balanced input unbalanced input resistances resistances constant c ext > 1nf at both c ext > 1nf at both in + v in(cm) C v ref(cm) in + and in C . can take and in C . can take large large source resistance source resistance. with negligible error unbalanced resistance results in an offset which can be calibrated varying c ext > 1nf at both in + minimize in + and in C v in(cm) C v ref(cm) and in C . can take large capacitors and avoid source resistance with large source impedance negligible error (< 5k recommended) will be insignificant (about 1% of their respective values over the entire temperature and voltage range). even for the most stringent applications, a one-time calibration operation may be sufficient. in addition to the input sampling charge, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na ( 10na max), results in a small offset shift. a 1k source resistance will create a 1 v typical and 10 v maximum offset voltage. reference current in a similar fashion, the ltc2481 samples the differential reference pins ref + and ref C transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. this current does not change the converter offset, but it may degrade the gain and inl performance. the effect of this current can be analyzed in two distinct situations. for relatively small values of the external reference capaci- tors (c ref < 1nf), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c ref will deteriorate the converter offset and gain performance without significant benefits of reference filter- ing and the user is advised to avoid them. larger values of reference capacitors (c ref > 1nf) may be required as reference filters in certain configurations. such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. in the following discussion, it is assumed the input and reference common mode are the same. using internal oscillator for 60hz mode, the typical differential reference resistance is 1m ? which generates a full-scale (v ref /2) gain error of 0.51ppm for each ohm of source resistance driving the ref + and ref C pins. for 50hz/60hz mode, the related difference resistance is 1.1m ? and the resulting full- scale error is 0.46ppm for each ohm of source resistance driving the ref + and ref C pins. for 50hz mode, the related difference resistance is 1.2m ? and the resulting full-scale error is 0.42ppm for each ohm of source resistance driving the ref + and ref C pins. when ca0/f 0 is driven by an applicatio s i for atio wu uu the magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are used for the external source impedance seen by in + and in C , the expected drift of the dynamic current and offset
25 ltc2481 2481f applicatio s i for atio wu uu figure 20. inl vs differential input voltage and reference source resistance for c ref > 1 f v in /v ref (v) C 0.5 inl (ppm of v ref ) 2 6 10 0.3 2481 f21 C2 C6 0 4 8 C4 C8 C10 C 0.3 C 0.1 0.1 0.5 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25 c c ref = 10 f r = 1k r = 100 ? r = 500 ? external oscillator with a frequency f eosc (external conver- sion clock operation), the typical differential reference resis- tance is 0.30 ? 10 12 /f eosc ? and each ohm of source resistance driving the ref + or ref C pins will result in 1.67 ? 10 C6 ? f eosc ppm gain error. the typical +fs and Cfs errors for various combinations of source resistance seen by the ref + or ref C pins and external capacitance connected to that pin are shown in figures 16-19. in addition to this gain error, the converter inl perfor- mance is degraded by the reference source impedance. the inl is caused by the input dependent terms Cv in 2 /(v ref ? r eq ) C (0.5 ? v ref ? d t )/r eq in the reference pin current as expressed in figure 12. when using internal oscillator and 60hz mode, every 100 ? of reference source resistance translates into about 0.67ppm additional inl r source ( ? ) 0 Cfs error (ppm) C30 C10 10 10k 2481 f18 C50 C70 C40 C20 0 C60 C80 C90 10 100 1k 100k v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf figure 17. ?s error vs r source at ref + or ref (small c ref ) r source ( ? ) 0 +fs error (ppm) 50 70 90 10k 2481 f17 30 10 40 60 80 20 0 C10 10 100 1k 100k v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf figure 16. +fs error vs r source at ref + or ref (small c ref ) figure 18. +fs error vs r source at ref + or ref (large c ref ) r source ( ? ) 0 +fs error (ppm) 300 400 500 800 2481 f19 200 100 0 200 400 600 1000 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v t a = 25 c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f r source ( ? ) 0 Cfs error (ppm) C200 C100 0 800 2481 f20 C300 C400 C500 200 400 600 1000 v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v t a = 25 c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f figure 19. ?s error vs r source at ref + or ref (large c ref )
26 ltc2481 2481f applicatio s i for atio wu uu error. when using internal oscillator and 50hz/60hz mode, every 100 ? of reference source resistance translates into about 0.61ppm additional inl error. when using internal oscillator and 50hz mode, every 100 ? of reference source resistance translates into about 0.56ppm additional inl error. when ca0/f 0 is driven by an external oscillator with a frequency f eosc , every 100 ? of source resistance driv- ing ref + or ref C translates into about 2.18 ? 10 C6 ? f eosc ppm additional inl error. figure 20 shows the typi- cal inl error due to the source resistance driving the ref + or ref C pins when large c ref values are used. the user is advised to minimize the source impedance driving the ref + and ref C pins. in applications where the reference and input common mode voltages are different, extra errors are introduced. for every 1v of the reference and input common mode voltage difference (v refcm C v incm ) and a 5v reference, each ohm of reference source resistance introduces an extra (v refcm C v incm )/(v ref ? r eq ) full-scale gain error, which is 0.074ppm when using internal oscillator and 60hz mode. when using internal oscillator and 50hz/60hz mode, the extra full-scale gain error is 0.067ppm. when using internal oscillator and 50hz mode, the extra gain error is 0.061ppm. if an external clock is used, the corre- sponding extra gain error is 0.24 ? 10 C6 ? f eosc ppm. the magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capaci- tors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. such a specification can also be easily achieved by an external clock. when relatively stable resistors (50ppm/ c) are used for the external source impedance seen by v ref + and v ref C , the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). even for the most stringent applications a one-time calibration operation may be sufficient. in addition to the reference sampling charge, the reference pins esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na ( 100na max), results in a small gain error. a 100 ? source resistance will create a 0.05 v typical and 5 v maximum full-scale error. output data rate (readings/sec) C10 offset error (ppm of v ref ) 10 30 50 0 20 40 20 40 60 80 2481 f22 100 10 030507090 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v ca0/f 0 = ext clock t a = 85 c t a = 25 c output data rate (readings/sec) 0 0 +fs error (ppm of v ref ) 500 1500 2000 2500 3500 10 50 70 2481 f23 1000 3000 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v ca0/f 0 = ext clock t a = 85 c t a = 25 c output data rate (readings/sec) 0 C3500 Cfs error (ppm of v ref ) C3000 C2000 C1500 C1000 0 10 50 70 2481 f24 C2500 C500 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v ca0/f 0 = ext clock t a = 85 c t a = 25 c figure 21. offset error vs output data rate and temperature figure 22. +fs error vs output data rate and temperature figure 23. ?s error vs output data rate and temperature
27 ltc2481 2481f third, an increase in the frequency of the external oscillator above 1mhz (a more than 3x increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. this will result in a progressive degradation in the converter accuracy and linearity. typi- cal measured performance curves for output data rates up to 100 readings per second are shown in figures 21 to 28. in order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. in certain circumstances, a reduc- tion of the differential reference voltage may be beneficial. input bandwidth the combined effect of the internal sinc 4 digital filter and of the analog and digital autocalibration circuits deter- mines the ltc2481 input bandwidth. when the internal oscillator is used with the notch set at 60hz, the 3db input bandwidth is 3.63hz. when the internal oscillator is used with the notch set at 50hz, the 3db input bandwidth is 3.02hz. if an external conversion clock generator of fre- quency f eosc is connected to the ca0/f 0 pin, the 3db input bandwidth is 11.8 ? 10 C6 ? f eosc . due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3db frequency. when the internal oscillator is used, the shape of the ltc2481 input bandwidth is shown in figure 29. when an external oscillator of frequency f eosc is used, the shape of the ltc2481 input bandwidth can be derived from figure 29, 60hz mode curve in which the horizontal axis is scaled by f eosc /307200. the conversion noise (600nv rms typical for v ref = 5v) can be modeled by a white noise source connected to a noise free converter. the noise spectral density is 47nv hz for an infinite bandwidth source and 64nv hz for a single 0.5mhz pole source. from these numbers, it is clear that particular attention must be given to the design of external amplification circuits. such circuits face the simultaneous requirements of very low bandwidth (just a few hz) in order to reduce the output referred noise and relatively high applicatio s i for atio wu uu output data rate when using its internal oscillator, the ltc2481 produces up to 7.5 samples per second (sps) with a notch frequency of 60hz, 6.25sps with a notch frequency of 50hz and 6.82sps with the 50hz/60hz rejection mode. the actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. when oper- ated with an external conversion clock (ca0/f 0 connected to an external oscillator), the ltc2481 output data rate can be increased as desired. the duration of the conversion phase is 41036/f eosc . if f eosc = 307.2khz, the converter behaves as if the internal oscillator is used and the notch is set at 60hz. an increase in f eosc over the nominal 307.2khz will translate into a proportional increase in the maximum output data rate. the increase in output rate is neverthe- less accompanied by three potential effects, which must be carefully considered. first, a change in f eosc will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. in many applications, the subsequent perfor- mance degradation can be substantially reduced by relying upon the ltc2481s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. the user should avoid single-ended input filters and should main- tain a very high degree of matching and symmetry in the circuits driving the in + and in C pins. second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. if large external input and/or reference capacitors (c in , c ref ) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter perfor- mance for any value of f eosc . if small external input and/or reference capacitors (c in , c ref ) are used, the effect of the external source resistance upon the ltc2481 typical per- formance can be inferred from figures 14, 15, 16 and 17 in which the horizontal axis is scaled by 307200/f eosc .
28 ltc2481 2481f applicatio s i for atio wu uu output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 50 70 2481 f25 14 22 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v ca0/f 0 = ext clock res = log 2 (v ref /noise rms ) t a = 85 c t a = 25 c output data rate (readings/sec) 0 C10 offset error (ppm of v ref ) C5 5 10 20 10 50 70 2481 f27 0 15 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v ca0/f 0 = ext clock t a = 25 c figure 24. resolution (noise rms 1lsb) vs output data rate and temperature figure 26. offset error vs output data rate and reference voltage figure 28. resolution (inl max 1lsb) vs output data rate and reference voltage output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2481 f29 14 20 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v in = 0v ca0/f 0 = ext clock t a = 25 c res = log 2 (v ref /inl max ) v cc = 5v, v ref = 2.5v v cc = v ref = 5v output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2481 f26 14 20 40 90 100 20 30 60 80 t a = 85 c t a = 25 c v in(cm) = v ref(cm) v cc = v ref = 5v ca0/f 0 = ext clock res = log 2 (v ref /inl max ) figure 25. resolution (inl max 1lsb) vs output data rate and temperature figure 27. resolution (noise rms 1lsb) vs output data rate and reference voltage output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 50 70 2481 f28 14 22 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v in = 0v ca0/f 0 = ext clock t a = 25 c res = log 2 (v ref /noise rms ) v cc = 5v, v ref = 2.5v v cc = v ref = 5v bandwidth (at least 500khz) necessary to drive the input switched-capacitor network. a possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. when external amplifiers are driving the ltc2481, the adc input referred system noise calculation can be simplified by figure 30. the noise of an amplifier driving the ltc2481 input pin can be modeled as a band limited white noise source. its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency f i . the amplifier noise spectral density is n i . from figure 30, using f i as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth
29 ltc2481 2481f applicatio s i for atio wu uu freq i of the input driving amplifier. this bandwidth in- cludes the band limiting effects of the adc internal calibration and filtering. the noise of the driving ampli- fier referred to the converter input and including all these effects can be calculated as n = n i ? freq i . the total system noise (referred to the ltc2481 input) can now be obtained by summing as square root of sum of squares the three adc input referred noise sources: the ltc2481 internal noise, the noise of the in + driving amplifier and the noise of the in C driving amplifier. if the ca0/f 0 pin is driven by an external oscillator of frequency f eosc , figure 30 can still be used for noise calculation if the x-axis is scaled by f eosc /307200. for large values of the ratio f eosc /307200, the figure 30 plot accuracy begins to decrease, but at the same time the ltc2481 noise floor rises and the noise contribution of the driving amplifiers lose significance. normal mode rejection and antialiasing one of the advantages delta-sigma adcs offer over con- ventional adcs is on-chip digital filtering. combined with a large oversampling ratio, the ltc2481 significantly simplifies antialiasing filter requirements. additionally, the input current cancellation feature of the ltc2481 allows external lowpass filtering without degrading the dc performance of the device. the sinc 4 digital filter provides greater than 120db nor- mal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ). the ltc2481s autocalibration circuits further sim- plify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. independent of the operating mode, f s = 256 ? f n = 2048 ? f outmax where f n is the notch frequency and f outmax is the maximum output data rate. in the internal oscillator mode with a 50hz notch setting, f s = 12800hz, with 50hz/60hz rejection, f s = 13960hz and with a 60hz notch setting f s = 15360hz. in the external oscillator mode, f s = f eosc /20. the performance of the normal mode rejection is shown in figures 31 and 32. in 1x speed mode, the regions of low rejection occurring at integer multiples of f s have a very narrow bandwidth. magnified details of the normal mode rejection curves are differential input signal frequency (hz) 0 input signal attenuation (db) C3 C2 C1 0 4 2481 f30 C4 C5 C6 1 2 3 5 50hz mode 60hz mode 50hz and 60hz mode figure 29. input signal using the internal oscillator input noise source single pole equivalent bandwidth (hz) 1 input referred noise equivalent bandwidth (hz) 10 0.1 1 10 100 1k 10k 100k 1m 2481 f31 0.1 100 50hz mode 60hz mode figure 30. input refered noise equivalent bandwidth of an input connected white noise source shown in figure 33 (rejection near dc) and figure 34 (rejection at f s = 256f n ) where f n represents the notch frequency. these curves have been derived for the exter- nal oscillator mode but they can be used in all operating modes by appropriately selecting the f n value. the user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by figures 35, 36 and 37. typical measured values of the normal mode rejection of the ltc2481 operating with an internal oscillator and a 60hz notch setting are shown in figure 35 superimposed over the theoretical calculated curve. similarly, the measured normal mode rejection of the ltc2481 for the 50hz rejection mode and 50hz/60hz rejection mode are shown in figures 36 and 37.
30 ltc2481 2481f applicatio s i for atio wu uu differential input signal frequency (hz) 0f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s 11f s 12f s input normal mode rejection (db) 2481 f32 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 figure 31. input normal mode rejection, internal oscillator and 50hz notch mode differential input signal frequency (hz) 0f s input normal mode rejection (db) 2481 f33 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s figure 32. input normal mode rejection at dc as a result of these remarkable normal mode specifica- tions, minimal (if any) antialias filtering is required in front of the ltc2481. if passive rc components are placed in front of the ltc2481, the input dynamic current should be considered (see input current section). in this case, the differential input current cancellation feature of the ltc2481 allows external rc networks without significant degrada- tion in dc performance. traditional high order delta-sigma modulators, while pro- viding very good linearity and resolution, suffer from potential instabilities at large input signal levels. the pro- prietary architecture used for the ltc2481 third order modulator resolves this problem and guarantees a predict- able stable behavior at input signal levels of up to 150% of full scale. in many industrial applications, it is not uncom- mon to have to measure microvolt level signals superim- posed on volt level perturbations and the ltc2481 is eminently suited for such tasks. when the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. with a reference voltage v ref = 5v, the ltc2481 has a full-scale differential input range of 5v peak-to-peak. figures 38 and 39 show measurement results for the ltc2481 normal mode rejec- tion ratio with a 7.5v peak-to-peak (150% of full scale) input signal superimposed over the more traditional nor- mal mode rejection ratio results obtained with a 5v peak- to-peak (full scale) input signal. in figure 38, the ltc2481 uses the internal oscillator with the notch set at 60hz and in figure 39 it uses the internal oscillator with the notch set at 50hz. it is clear that the ltc2481 rejection performance input signal frequency (hz) input normal mode rejection (db) 2481 f34 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n f n = f eosc/5120 input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2481 f35 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 figure 34. input normal mode rejection at f s = 256f n figure 33. input normal mode rejection at dc
31 ltc2481 2481f applicatio s i for atio wu uu input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2481 f36 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25 c measured data calculated data figure 35. input normal mode rejection vs input frequency with input perturbation of 100% full scale (60hz notch) figure 36. input normal mode rejection vs input frequency with input perturbation of 100% full scale (50hz notch) input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2481 f37 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25 c measured data calculated data figure 37. input normal mode rejection vs input frequency with input perturbation of 100% full scale (50hz/60hz mode) input frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 normal mode rejection (db) 2481 f38 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25 c measured data calculated data input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2481 f39 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v incm = 2.5v t a = 25 c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) figure 38. measured input normal mode rejection vs input frequency with input perturbation of 150% full scale (60hz notch) figure 39. measured input normal mode rejection vs input frequency with input perturbation of 150% full scale (50hz notch) input frequency (hz) 0 normal mode rejection (db) 2481 f40 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25 c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
32 ltc2481 2481f applicatio s i for atio wu uu figure 44. calibration setup scl sda ca1 ca0/f 0 6 7 9 10 v cc 5v ltc2481 ref + gnd in C in + 1 isothermal 2 c7 0.1 f 1.7k c8 1 f 4 r2 2k r7 8k 6 2 5 4 r8 1k 5 2481 f45 26.3c type k thermocouple jack (omega mpj-k-f) 8 3 ref C in out g1 nc1m4v0 trim gnd lt1236 + 1.7k differential input signal frequency (hz) 48 C70 C80 C90 C100 C110 C120 C130 C140 54 58 2481 f44 50 52 56 60 62 normal mode rejection (db) no average with running average figure 43. input normal mode rejection 2x speed mode input frequency (hz) 0 normal mode rejection (db) 50 100 125 225 2481 f43 25 75 150 175 200 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v incm = 2.5v v in(p-p) = 5v t a = 25 c measured data calculated data figure 42. input normal mode rejection vs input frequency, 2x speed mode and 50hz/60hz mode input signal frequency (f n ) input normal rejection (db) 2481 f42 0 C20 C40 C60 C80 C100 C120 250 248 252 254 256 258 260 262 264 figure 41. input normal mode rejection 2x speed mode input signal frequency (f n ) input normal rejection (db) 2481 f41 0 C20 C40 C60 C80 C100 C120 0 f n 2f n 3f n 4f n 5f n 6f n 7f n 8f n figure 40. input normal mode rejection 2x speed mode
33 ltc2481 2481f applicatio s i for atio wu uu is maintained with no compromises in this extreme situa- tion. when operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings. using the 2x speed mode of the ltc2481, the device bypasses the digital offset calibration operation to double the output data rate. the superior normal mode rejection is maintained as shown in figures 31 and 32. however, the magnified details near dc and f s = 256f n are different, see figures 40 and 41. in 2x speed mode, the bandwidth is 11.4hz for the 50hz rejection mode, 13.6hz for the 60hz rejection mode and 12.4hz for the 50hz/60hz rejection mode. typical measured values of the normal mode rejection of the ltc2481 operating with the internal oscil- lator and 2x speed mode is shown in figure 42. when the ltc2481 is configured in 2x speed mode, by performing a running average, a sinc 1 notch is combined with the sinc 4 digital filter, yielding the normal mode rejection identical as that for the 1x speed mode. the averaging operation still keeps the output rate with the following algorithm: result 1 = average (sample 0, sample 1) result 2 = average (sample 1, sample 2) result n = average (sample n C 1, sample n) the main advantage of the running average is that it achieves simultaneous 50hz/60hz rejection at twice the effective output rate, as shown in figure 43. the raw output data provides a better than 70db rejection over 48hz to 62.4hz, which covers both 50hz 2% and 60hz 2%. with running average on, the rejection is better than 87db for both 50hz 2% and 60hz 2%. complete thermocouple measurement system with cold junction compensation the ltc2481 is ideal for direct digitization of thermocouples and other low voltage output sensors. the input has a typical offset error of 500nv (2.5 v max) offset drift of 10nv/ c and a noise level of 600nv rms . the input span may be optimized for various sensors by setting the gain of the pga. using an external 5v reference with a pga gain of 64 gives a 78mv input rangeperfect for thermocouples. figure 45 (page 39 of this data sheet) is a complete type k thermocouple meter. the only signal conditioning is a simple surge protection network. in any thermocouple meter, the cold junction temperature sensor must be at the same temperature as the junction between the thermo- couple materials and the copper printed circuit board traces. the tiny ltc2481 can be tucked neatly underneath an omega mpj-k-f thermocouple socket ensuring close thermal coupling. the ltc2481s 1.4mv/ c ptat circuit measures the cold junction temperature. once the thermocouple voltage and cold junction temperature are known, there are many ways of calculating the thermocouple temperature including a straight-line approximation, lookup tables or a polynomial curve fit. calibration is performed by applying an accurate 500mv to the adc input derived from an lt ? 1236 refer- ence and measuring the local temperature with an accu- rate thermometer as shown in figure 44. in calibration mode, the up and down buttons are used to adjust the local temperature reading until it matches an accurate ther- mometer. both the voltage and temperature calibration are easily automated. the complete microcontroller code for this application is available on the ltc2481 product webpage at: http://www.linear.com it can be used as a template for may different instruments and it illustrates how to generate calibration coefficients for the onboard temperature sensor. extensive comments detail the operation of the program. the read_ltc2481() function controls the operation of the ltc2481 and is listed below for reference.
34 ltc2481 2481f /* ltc248x.h processor setup and lots of useful defines for configuring the ltc2481 and ltc2485. */ #include <16f73.h> // device #use delay(clock=6000000) // 6mhz clock //#fuses nowdt,hs, put, noprotect, nobrownout // configuration fuses #rom 0x2007={0x3f3a} // equivalent and more reliable fuse config. #use i2c(master, sda=pin_c5, scl=pin_c3, slow)// set up i2c port #include "pcm73a.h" // various defines #include "lcd.c" // lcd driver functions // useful defines for the ltc2481 and ltc2485 - or them together to make the // 8 bit config word. #define read 0x01 // bitwise or with address for read or write #define write 0x00 #define ltc248xaddr 0b01001000 // the one and only ltc248x in this circuit, // with both address lines floating. // select gain - 1 to 256 (also depends on speed setting) #define gain1 0b00000000 // g = 1 (spd = 0), g = 1 (spd = 1) #define gain2 0b00100000 // g = 4 (spd = 0), g = 2 (spd = 1) #define gain3 0b01000000 // g = 8 (spd = 0), g = 4 (spd = 1) #define gain4 0b01100000 // g = 16 (spd = 0), g = 8 (spd = 1) #define gain5 0b10000000 // g = 32 (spd = 0), g = 16 (spd = 1) #define gain6 0b10100000 // g = 64 (spd = 0), g = 32 (spd = 1) #define gain7 0b11000000 // g = 128 (spd = 0), g = 64 (spd = 1) #define gain8 0b11100000 // g = 256 (spd = 0), g = 128 (spd = 1) // select adc source - differential input or ptat circuit #define vin 0b00000000 #define ptat 0b00001000 // select rejection frequency - 50, 55, or 60hz #define r50 0b00000010 #define r55 0b00000000 #define r60 0b00000100 // speed settings is bit 7 in the 2nd byte #define slow 0b00000000 // slow output rate with autozero #define fast 0b00000001 // fast output rate with no autozero applicatio s i for atio wu uu
35 ltc2481 2481f applicatio s i for atio wu uu /* ltc2481.c basic voltmeter test program for ltc2481 reads ltc2481 input at gain = 1, 1x speed mode, converts to volts, and prints voltage to a 2 line by 16 character lcd display. mark thoren linear technonlgy corporation june 23, 2005 written for ccs pcm compiler, version 3.182 */ #include "ltc248x.h" /*** read_ltc2481() ************************************************************ this is the function that actually does all the work of talking to the ltc2481. arguments: addr - device address config - configuration bits for next conversion returns: zero if conversion is in progress, 32 bit signed integer with lower 8 bits clear, 24 bit ltc2481 output word in the upper 24 bits. data is left-justified for compatibility with the 24 bit ltc2485. the i2c_xxxx() functions do the following: void i2c_start(void): generate an i2c start or repeat start condition void i2c_stop(void): generate an i2c stop condition char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device these functions are very compiler specific, and can use either a hardware i2c port or software emulation of an i2c port. this example uses software emulation. a good starting point when porting to other processors is to write your own i2c functions. note that each processor has its own way of configuring the i2c port, and different compilers may or may not have built-in functions for the i2c port. when in doubt, you can always write a "bit bang" function for troubleshooting purposes. the "fourbytes" structure allows byte access to the 32 bit return value: struct fourbytes // define structure of four consecutive bytes { // to allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // the make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. }; also note that the lower 4 bits are the configuration word from the previous conversion.
36 ltc2481 2481f applicatio s i for atio wu uu *******************************************************************************/ signed int32 read_ltc2481(char addr, char config) { struct fourbytes // define structure of four consecutive bytes { // to allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // the make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. }; union // adc_code.bits32 all 32 bits { // adc_code.by.te0 byte 0 signed int32 bits32; // adc_code.by.te1 byte 1 struct fourbytes by; // adc_code.by.te2 byte 2 } adc_code; // adc_code.by.te3 byte 3 // start communication with ltc2481: i2c_start(); if(i2c_write(addr | write))// if no acknowledge, return zero { i2c_stop(); return 0; } i2c_write(config); i2c_start(); i2c_write(addr | read); adc_code.by.te3 = i2c_read(); adc_code.by.te2 = i2c_read(); adc_code.by.te1 = i2c_read(); adc_code.by.te0 = 0; i2c_stop(); return adc_code.bits32; } // end of read_ltc2481() /*** initialize() ************************************************************** basic hardware initialization of controller and lcd, send hello message to lcd *******************************************************************************/ void initialize(void) { // general initialization stuff. setup_adc_ports(no_analogs); setup_adc(adc_off); setup_counters(rtcc_internal,rtcc_div_1); setup_timer_1(t1_disabled); setup_timer_2(t2_disabled,0,1); // this is the important part - configuring the spi port setup_spi(spi_master|spi_l_to_h|spi_clk_div_16|spi_ss_disabled); // fast spi clock ckp = 0; // set up clock edges - clock idles low, data changes on cke = 1; // falling edges, valid on rising edges.
37 ltc2481 2481f applicatio s i for atio wu uu lcd_init(); // initialize lcd delay_ms(6); printf(lcd_putc, "hello!"); // obligatory hello message delay_ms(500); // for half a second } // end of initialize() *** main() ******************************************************************** main program initializes microcontroller registers, then reads the ltc2481 repeatedly *******************************************************************************/ void main() { signed int32 x; // integer result from ltc2481 float voltage; // variable for floating point math int16 timeout; initialize(); // hardware initialization while(1) { delay_ms(1); // pace the main loop to something more than 1 ms // this is a basic error detection scheme. the ltc248x will never take more than // 163.5ms, 149.9ms, or 136.5ms to complete a conversion in the 50hz, 55hz, and 60hz // rejection modes, respectively. // if read_ltc248x() does not return non-zero within this time period, something // is wrong, such as an incorrect i2c address or bus conflict. if((x = read_ltc2481(ltc248xaddr, gain1 | vin | r55)) != 0) { // no timeout, everything is okay timeout = 0; // reset timer x &= 0xffffffc0; // clear config bits so they don't affect math x ^= 0x80000000; // invert msb, result is 2's complement voltage = (float) x; // convert to float voltage = voltage * 5.0 / 2147483648.0;// multiply by vref, divide by 2^31 lcd_putc('\f'); // clear screen lcd_gotoxy(1,1); // goto home position printf(lcd_putc, "v %01.4f", voltage); // display voltage } else { ++timeout; } if(timeout > 200) { timeout = 200; // prevent rollover lcd_gotoxy(1,1); printf(lcd_putc, "error - timeout"); delay_ms(500); } } // end of main loop } // end of main()
38 ltc2481 2481f dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd10) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc u package descriptio
39 ltc2481 2481f scl sda cao/f o 6 7 10 18 17 16 15 14 13 12 11 28 27 26 25 24 23 22 21 7 6 5 4 3 2 v cc 5v ltc2481 ref ref C in C in + 3 isothermal 2 c7 0.1 f c8 1 f c6 0.1 f 4 r2 2k 5 type k thermocouple jack (omega mpj-k-f) 5v 5v 3 8 9 gnd ca1 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 ra5 ra4 ra3 ra2 ra1 ra0 v dd osc1 osc2 mclr 20 9 10 1 5v 5v y1 6mhz r1 10k d1 bat54 v ss 9 2481 f46 v ss 19 pic16f73 d7 d6 d5 d4 en rw rs r5 10k r4 10k r3 10k r6 5k 2 1 3 2 1 5v calibrate contrast gnd d0 v cc d1 d2 d3 2 16 character lcd display (optrex dmc162488 or similar) down up 1.7k 1.7k typical applicatio u figure 45. complete type k thermocouple meter information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
40 ltc2481 2481f part number description comments lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/ c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/ c max drift lt1790 micropower sot-23 low dropout reference family 0.05% max initial accuracy, 10ppm/ c max drift ltc2400 24-bit, no latency ? adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200 a ltc2410 24-bit, no latency ? adc with differential inputs 0.8 v rms noise, 2ppm inl ltc2411/ltc2411-1 24-bit, no latency ? adcs with differential inputs in msop 1.45 v rms noise, 4ppm inl, simultaneous 50hz/60hz rejection (ltc2411-1) ltc2413 24-bit, no latency ? adc with differential inputs simultaneous 50hz/60hz rejection, 800nv rms noise ltc2415/ 24-bit, no latency ? adcs with 15hz output rate pin compatible with the ltc2410 ltc2415-1 ltc2414/ltc2418 8-/16-channel 24-bit, no latency ? adcs 0.2ppm noise, 2ppm inl, 3ppm total unadjusted errors 200 a ltc2440 high speed, low noise 24-bit ? adc 3.5khz output rate, 200nv noise, 24.6 enobs ltc2480 16-bit ? adc with easy drive inputs, 600nv noise, pin compatible with ltc2482/ltc2484 programmable gain, and temperature sensor ltc2482 16-bit ? adc with easy drive inputs pin compatible with ltc2480/ltc2484 ltc2483 16-bit ? adc with easy drive inputs, i 2 c interface pin compatible with ltc2481/ltc2483 ltc2484 24-bit ? adc with easy drive inputs pin compatible with ltc2480/ltc2482 ltc2485 24-bit ? adc with easy drive inputs, i 2 c interface and pin compatible with ltc2481/ltc2483 temperature sensor related parts ? linear technology corporation 2005 lt/lwi/tp 0805 500 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com

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